
library IEEE;
use IEEE.std_logic_1164.all;


entity fpgatester is
  port (
    clk : in std_logic; --
    
    reset : in std_logic; --button
    direction : in std_logic; --switch
    counter_reset : in std_logic; --button
    
    motor : out std_logic
  );
end fpgatester;

architecture structural of fpgatester is
  component counter 
	port (	clk		: in	std_logic;
		reset		: in	std_logic;

		count_out	: out	std_logic_vector (19 downto 0)
	);
  end component;
  component pwm_generator 
	port (	clk		: in	std_logic;
		reset		: in	std_logic;
		direction	: in	std_logic;
		count_in	: in	std_logic_vector (19 downto 0);
		
		

		pwm		: out	std_logic
	);
  end component;
signal count : std_logic_vector(19 downto 0);

  
begin
  lbl_count: counter PORT MAP (clk, counter_reset, count);
  lbl_pwml: pwm_generator PORT MAP ( clk, 
              reset, direction, count, motor);
end structural;
